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may 2016 docid023563 rev 5 1 / 38 this is information on a p roduct in full production. www.st.com tsz121, tsz122, tsz124 very high accuracy (5 v) zero drift micropower 5 v operational amplifiers datasheet - production data features very high accuracy and stability: offset voltage 5 v max at 25 c, 8 v over full temperature range ( - 40 c to 125 c) rail - to - rail input and output low supply voltage: 1.8 - 5.5 v low power consumption: 40 a max. at 5 v gain bandwidth product: 400 k hz high tolerance to esd: 4 kv hbm extended temperature range: - 40 to 125 c micro - packages: sc70 - 5, dfn8 2x2, and qfn16 3x3 benefits higher accuracy without calibra tion accuracy virtually unaffected by temperature change related products see tsv711 or tsv731 for continuous - time precision amplifiers applications battery - powered applications po rtable devices signal conditioning medical instrumentation description the tsz12x series of high precision operational amplifiers offer very low input offset voltages with virtually zero drift. tsz121 is the single version, tsz122 the dual version, and tsz124 the quad version, with pinouts compatible with industry standards. the tsz12x series offers rail - to - rail input and output, excellent speed/power consumption ratio, and 400 khz gain bandwidth product, while consuming less than 40 a at 5 v. the devices also feature an ultra - low input bias current. these features make the tsz12x family ideal for sensor interfaces, battery - powered applications and por table applications.
contents tsz121, tsz122, tsz124 2 / 38 docid023563 rev 5 contents 1 package pin connections ................................ ................................ 3 2 absolute maximum ratings and operating conditions ................. 4 3 electrical characteristics ................................ ................................ 5 4 electrical characteristic curves ................................ .................... 11 5 application information ................................ ................................ 17 5.1 operation theory ................................ ................................ ............. 17 5.1.1 time domain ................................ ................................ ..................... 17 5.1.2 frequency domain ................................ ................................ ............ 18 5.2 operating voltages ................................ ................................ .......... 19 5.3 input pin voltage ranges ................................ ................................ .. 19 5.4 rail - to - rail input ................................ ................................ ............... 19 5.5 input offset voltage drift over temperature ................................ ....... 20 5.6 rail - to - rail output ................................ ................................ ............. 20 5.7 capacitive load ................................ ................................ ................ 20 5.8 pcb layout recommendations ................................ ......................... 21 5.9 optimized application recommendation ................................ .......... 21 5.10 emi rejection ration (emirr) ................................ .......................... 22 5.11 application examples ................................ ................................ ...... 22 5.11.1 oxygen sensor ................................ ................................ ................. 22 5.11.2 precision instrumentation amplifier ................................ .................. 23 5.11.3 low - side current sensing ................................ ................................ .. 24 6 package information ................................ ................................ ..... 25 6.1 sc70 - 5 (or sot323 - 5) package information ................................ ... 26 6.2 sot23 - 5 package information ................................ ........................ 2 7 6.3 dfn8 2x2 package information ................................ ....................... 29 6.4 miniso8 package information ................................ ......................... 31 6.5 so8 package information ................................ ................................ 32 6.6 qfn16 3x3 package information ................................ ..................... 33 6.7 tssop14 package information ................................ ....................... 35 7 ordering information ................................ ................................ ..... 36 8 revision history ................................ ................................ ............ 37
tsz121, tsz122, tsz124 pa ckage pin connections docid023563 rev 5 3 / 38 1 package pin connections figure 1 : pin connections for each package (top view) 1. the exposed pads of the dfn8 2x2 and the qfn16 3x3 can be connected to vcc - or left floating.
absolute maximum ratings and operating conditions tsz121, tsz122, tsz124 4 / 38 docid023563 rev 5 2 absolute maximum ratings and operating conditions table 1: absolute maximum ratings (amr) symbol parameter value unit v cc supply voltage (1) 6 v v id differential input voltage (2) v cc v in input voltage (3) (v cc - ) - 0.2 to (v cc+ ) + 0.2 i in input current (4) 10 ma t stg storage temperature - 65 to 150 c t j maximum junction temperature 150 r thja thermal resistance junction to ambient (5) (6) sc70 - 5 205 c/w sot23 - 5 250 dfn8 2x2 57 miniso8 190 so8 125 qfn16 3x3 39 tssop14 100 esd hbm: human body model (7) 4 kv mm: machine model (8) 300 v cdm: charged device model (9) 1.5 kv latch - up immunity 200 ma notes: (1) all voltage values, except the differential voltage are with respect to the network ground terminal. (2) the differential voltage is the non - inverting input terminal with respect to the inverting input terminal. (3) v cc - v in must not exceed 6 v, vin must not exceed 6 v (4) input current must be limited by a resistor in series with the inputs. (5) r th are typical values. (6) short - circuits can cause excessive heating and destructive dissipation. (7) human body model: 100 pf discharged through a 1.5 k resistor between two pins of the device, done for all couples of pin combinations with other pins floating. (8) machine model: a 200 pf cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ), done for all couples of pin combinations with other pins floating. (9) charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground. table 2: operating conditions symbol parameter value unit v cc supply voltage 1.8 to 5.5 v v icm common mode input voltage range (v cc - ) - 0.1 to (v cc+ ) + 0.1 t oper operating free air temperature range - 40 to 125 c
tsz121, tsz122, tsz124 electrical characteristics docid023563 rev 5 5 / 38 3 electrical characteristics table 3: electrical characteristics at vcc+ = 1.8 v with vcc - = 0 v, vicm = vcc/2, t = 25 c, and rl = 10 k connected to vcc/2 (unless otherwise sp ecified) symbol parameter conditions min. typ. max. unit dc performance v io input offset voltage t = 25 c 1 5 v - 40 c < t < 125 c 8 v io /t input offset voltage drift (1) - 40 c < t < 125 c 10 30 nv/c i ib input bias current (v out = v cc /2) t = 25 c 50 200 (2) pa - 40 c < t < 125 c 300 (2) i io input offset current (v out = v cc /2) t = 25 c 100 400 (2) - 40 c < t < 125 c 600 (2) cmr common mode rejection ratio, 20 log (v icm /v io ), v ic = 0 v to v cc , v out = v cc /2, r l > 1 m t = 25 c 110 122 db - 40 c < t < 125 c 110 a vd large signal voltage gain, v out = 0.5 v to (v cc - 0.5 v) t = 25 c 118 135 - 40 c < t < 125 c 110 v oh high - level output voltage t = 25 c 30 mv - 40 c < t < 125 c 70 v ol low - level output voltage t = 25 c 30 - 40 c < t < 125 c 70 i out i sink (v out = v cc ) t = 25 c 7 8 ma - 40 c < t < 125 c 6 i source (v out = 0 v) t = 25 c 5 7 - 40 c < t < 125 c 4 i cc supply current (per amplifier, v out = v cc /2, r l > 1 m) t = 25 c 28 40 a - 40 c < t < 125 c 40 ac performance gbp gain bandwidth product r l = 10 k, c l = 100 pf 400 khz f u unity gain frequency 300 ?m phase margin 55 degrees g m gain margin 17 db sr slew rate (3) 0.17 v/s t s setting time to 0.1 %, v in = 1 vp - p, r l = 10 k, c l = 100 pf 50 s e n equivalent input noise voltage f = 1 khz 60 nv/hz f = 10 khz 60 c s channel separation f = 100 hz 120 db
electrical characterist ics tsz121, tsz122, tsz124 6 / 38 docid023563 rev 5 symbol parameter conditions min. typ. max. unit t init initialization time t = 25 c 50 s - 40 c < t < 125 c 100 notes: (1) see section 5.5: "input offset voltage drift over temperature" . input offset measurements are performed on x100 gain configuration. the amplifiers and the gain setting resistors are at the same temperature. (2) guaranteed by design (3) slew rate value is calculated as the average between positive and negative slew rates.
tsz121, tsz122, tsz124 electrical characteristics docid023563 rev 5 7 / 38 table 4: electrical characteristics at vcc+ = 3.3 v with vcc - = 0 v, vicm = vcc/2, t = 25 c, and rl = 10 k connected to vcc/2 (unless otherwise specified) symbol parameter conditions min. typ. max. unit dc performance v io input offset voltage t = 25 c 1 5 v - 40 c < t < 125 c 8 v io /t input offset voltage drift (1) - 40 c < t < 125 c 10 30 nv/c i ib input bias current (v out = v cc /2) t = 25 c 60 200 (2) pa - 40 c < t < 125 c 300 (2) i io input offset current (v out = v cc /2) t = 25 c 120 400 (2) - 40 c < t < 125 c 600 (2) cmr common mode rejection ratio, 20 log (v icm /v io ), v ic = 0 v to v cc , v out = v cc /2, r l > 1 m t = 25 c 115 128 db - 40 c < t < 125 c 115 a vd large signal voltage gain, v out = 0.5 v to (v cc - 0.5 v) t = 25 c 118 135 - 40 c < t < 125 c 110 v oh high - level output voltage t = 25 c 30 mv - 40 c < t < 125 c 70 v ol low - level output voltage t = 25 c 30 - 40 c < t < 125 c 70 i out i sink (v out = v cc ) t = 25 c 15 18 ma - 40 c < t < 125 c 12 i source (v out = 0 v) t = 25 c 14 16 - 40 c < t < 125 c 10 i cc supply current (per amplifier, v out = v cc /2, r l > 1 m) t = 25 c 29 40 a - 40 c < t < 125 c 40 ac performance gbp gain bandwidth product r l = 10 k, c l = 100 pf 400 khz f u unity gain frequency 300 ?m phase margin 56 degrees g m gain margin 19 db sr slew rate (3) 0.19 v/s t s setting time to 0.1 %, v in = 1 vp - p, r l = 10 k, c l = 100 pf 50 s e n equivalent input noise voltage f = 1 khz 40 nv/hz f = 10 khz 40 c s channel separation f = 100 hz 120 db t init initialization time t = 25 c 50 s - 40 c < t < 125 c 100
electrical characteristics tsz121, tsz122, tsz124 8 / 38 docid023563 rev 5 notes: (1) see section 5.5: "input offset voltage drift over temperature" . input offset measurements are performed on x100 gain configuration. the amplifiers and the gain setting resistors are at the same temperature. (2) guaranteed by design (3) slew rate value is calculated as the average between positive and negative slew rates.
tsz121, tsz122, tsz124 electrical characteristics docid023563 rev 5 9 / 38 table 5: electrical characteristics at vcc+ = 5 v with vcc - = 0 v, vicm = vcc/2, t = 25 c, and rl = 10 k connected to vcc/2 (unless other wise specified) symbol parameter conditions min. typ. max. unit dc performance v io input offset voltage t = 25 c 1 5 v - 40 c < t < 125 c 8 v io /t input offset voltage drift (1) - 40 c < t < 125 c 10 30 nv /c i ib input bias current (v out = v cc /2) t = 25 c 70 200 (2) pa - 40 c < t < 125 c 300 (2) i io input offset current (v out = v cc /2) t = 25 c 140 400 (2) - 40 c < t < 125 c 600 (2) cmr common mode rejection ratio, 20 log (v icm /v io ), v ic = 0 v to v cc , v out = v cc /2, r l > 1 m t = 25 c 115 136 db - 40 c < t < 125 c 115 svr supply voltage rejection ratio, 20 log (v cc /v io ), v cc = 1.8 v to 5.5 v, v out = v cc /2, r l > 1 m t = 25 c 120 140 - 40 c < t < 125 c 120 a vd large signal voltage gain, v out = 0.5 v to (v cc - 0.5 v) t = 25 c 120 135 - 40 c < t < 125 c 110 emirr (3) emi rejection rate = - 20 log (v rfpeak /v io ) v rf = 100 mv p , f = 400 mhz 84 v rf = 100 mv p , f = 900 mhz 87 v rf = 100 mv p , f = 1800 mhz 90 v rf = 100 mv p , f = 2400 mhz 91 v oh high - level output voltage t = 25 c 30 mv - 40 c < t < 125 c 70 v ol low - level output voltage t = 25 c 30 - 40 c < t < 125 c 70 i out i sink (v out = v cc ) t = 25 c 15 18 ma - 40 c < t < 125 c 14 i source (v out = 0 v) t = 25 c 14 17 - 40 c < t < 125 c 12 i cc supply current (per amplifier, v out = v cc /2, r l > 1 m) t = 25 c 31 40 a - 40 c < t < 125 c 40 ac performance gbp gain bandwidth product r l = 10 k, c l = 100 pf 400 khz f u unity gain frequency 300 ?m phase margin 53 degrees g m gain margin 19 db sr slew rate (4) 0.19 v/s
electrical characteri stics tsz121, tsz122, tsz124 10 / 38 docid023563 rev 5 symbol parameter conditions min. typ. max. unit t s setting time to 0.1 %, v in = 100 mvp - p, r l = 10 k, c l = 100 pf 10 s e n equivalent input noise voltage f = 1 khz 37 nv/hz f = 10 khz 37 c s channel separation f = 100 hz 120 db t init initialization time t = 25 c 50 s - 40 c < t < 125 c 100 notes: (1) see section 5.5: "input offset voltage drift over temperature" . input offset measurements are performed on x100 gain configuration. the amplifiers and the gain setting resistors are at the same temperature. (2) guaranteed by design (3) tested on sc70 - 5 package (4) slew rate value is calculated as the average between positive and negative slew rates.
tsz121, tsz122, tsz124 electrical characteristic curves docid023563 rev 5 11 / 38 4 electrical characteristic curves figure 2 : supply current vs. supply voltage figure 3 : input offset voltage distribution at vcc = 5 v figure 4 : input offset voltage distribution at vcc = 3.3 v figure 5 : input offset voltage distribution at vcc = 1.8 v figure 6 : vio temperature co - efficient distribution ( - 40 c to 25 c) figure 7 : vio temperature co - efficient distribution (25 c to 125 c)
electrical characteristic curves tsz121, tsz122, tsz124 12 / 38 docid023563 rev 5 figure 8 : input offset voltag e vs. supply voltage figure 9 : input offset voltage vs. input common - mode at vcc = 1.8 v figure 10 : input offset voltage vs. input common - mode at vcc = 2.7 v figure 11 : input offset voltage vs. input common - mode at vcc = 5.5 v figure 12 : input offset voltage vs. temperature figure 13 : voh vs. supply voltage
tsz121, tsz122, tsz124 electrical characteristic curves docid023563 rev 5 13 / 38 figure 14 : vol vs. supply voltage figure 15 : output current vs. output voltage at vcc = 1.8 v figure 16 : output current vs. output voltage at vcc = 5.5 v figure 17 : input bias current vs. common mode at vcc = 5 v figure 18 : input bias current vs. common mode at vcc = 1.8 v figure 19 : input bias current vs. temperature at vcc = 5 v
electrical characteristic curves tsz121, tsz122, tsz124 14 / 38 docid023563 rev 5 figure 20 : bode diagram at vcc = 1.8 v figure 21 : bode diagram at vcc = 2.7 v figure 22 : bode diagram at vcc = 5.5 v figure 23 : open loop gain vs. frequency figure 24 : positive slew rate vs. supply voltage figure 25 : negative slew rate vs. supply voltage
tsz121, tsz122, tsz124 electrical characteristic curves docid023563 rev 5 15 / 38 figure 26 : 0.1 hz to 10 hz noise figure 27 : noise vs. frequency figure 28 : noise vs. frequency and temperature figure 29 : output overshoot vs. load capacitance figure 30 : small signal figure 31 : large signal
electrical characteristic curves tsz121, tsz122, tsz124 16 / 38 docid023563 rev 5 figure 32 : positive overvoltage recovery at vcc = 1.8 v figure 33 : positive overvoltage recovery at vcc = 5 v figure 34 : negative overvoltage recovery at vcc = 1.8 v figure 35 : negative overvoltage recovery at vcc = 5 v figure 36 : psrr vs. frequency figure 37 : output impedance vs. frequency
tsz121, tsz122, tsz124 application information docid023563 rev 5 17 / 38 5 application information 5.1 operation theory the tsz121, tsz122, and tsz124 are h igh precision cmos devices. they achieve a low offset drift and no 1/f noise thanks to their chopper architecture. chopper - stabilized amps constantly correct low - frequency errors across the inputs of the amplifier. chopper - stabilized amplifiers can be expl ained with respect to: time domain frequency domain 5.1.1 time domain the basis of the chopper amplifier is realized in two steps. these steps are synchronized than ks to a clock running at 400 khz. figure 38 : block diagram in the time domain (step 1) figure 39 : block diagram in the time domain (step 2) figure 38: "block diagram i n the time domain (step 1)" shows step 1, the first clock cycle, where v io is amplified in the normal way. figure 39: "block diagram in the time domain (step 2)" shows step 2, the second clock cycle, where chop1 and chop2 s wap paths. at this time, the v io is amplified in a reverse way as compared to step 1. at the end of these two steps, the average v io is close to zero. the a2(f) amplifier has a small impact on the v io because the v io is expressed as the input offset and is consequently divided by a1(f). in the time domain, the offset part of the output signal before filtering is shown in figure 40: "vio cancellation principle" .
application information tsz121, tsz122, tsz124 18 / 38 docid023563 rev 5 figure 40 : vio cancellation principle the low pass filter averages the output value resulting in the cancellation of the v io offset. the 1/f noise can be considered as an offset in low frequency and it is canceled like the v io , thanks to the chopper technique. 5.1.2 frequency domain the frequency domain gives a more accurate vision of chopper - stabilized amplifier architecture. figure 41 : block diagram in the frequency domain the modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and demodulate it back after amplification. 1. according to figure 41: "block diag ram in the frequency domain" , the input signal v in is modulated once (chop1) so all the input signal is transposed to the high frequency domain. 2. the amplifier adds its own error (v io (output offset voltage) + the noise v n (1/f noise)) to this modulated si gnal. 3. this signal is then demodulated (chop2), but since the noise and the offset are modulated only once, they are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low frequency noise. consequently, the input signal is amplified with a very low offset and 1/f noise. 4. to get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented. to further suppress the remaining ripple down to a desired level, another low pass filter may be added externally on the output of the tsz121, tsz122, or tsz124 device.
tsz121, tsz122, tsz124 application information docid023563 rev 5 19 / 38 5.2 operating voltages tsz121, tsz122, and tsz124 devices can operate from 1.8 to 5.5 v. the parameters are fully specified for 1.8 v, 3.3 v, and 5 v power supplies. however, the parameters are very stable in the full v cc range and several characterization curves show the tsz121, tsz122, and tsz124 device characteris tics at 1.8 v and 5.5 v. additionally, the main specifications are guaranteed in extended temperature ranges from - 40 to 125 c. 5.3 input pin voltage ranges tsz121, tsz122, and tsz124 devices have internal esd diode protection on the inputs. these diodes are connected between the input and each supply rail to protect the input mosfets from electrical discharge. if the input pin voltage exceeds the power supply by 0.5 v, the esd diodes become conductive and excessive current can flow through them. without limitation this over current can damage the device. in this case, it is important to limit the current to 10 ma, by adding resistance on the input pin, a s described in figure 42: "input current limitation" . figure 42 : input current limitation 5.4 rail - to - rail input tsz121, tsz122, and tsz124 devices have a rail - to - rail input, and the input common mode range is extended from (v cc - ) - 0.1 v to (v cc+ ) + 0.1 v.
application information tsz121, tsz122, tsz124 20 / 38 docid023563 rev 5 5.5 input o ffset voltage drift over temperature the maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 c. the operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. the signal chain accuracy at 25 c can be c ompensated during production at application level. the maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. the maximum input voltage drift over temperature is computed using equation 1 . equation 1 where t = - 40 c and 125 c. the tsz121, tsz122, and tsz124 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a c pk (process capability index) greater than 1.3. 5.6 r ail - to - rail output the operational amplifier output levels can go close to the rails: to a maximum of 30 mv above and below the rail when connected to a 10 k resistive load to v cc /2. 5.7 capacitive load driving large capacitive loads can cause stability problems. increasing the load capacitance produces gain peak ing in the frequency response, with overshoot and ringing in the step response. it is usually considered that with a gain peaking higher than 2.3 db an op amp might become unstable. generally, the unity gain configuration is the worst case for stability an d the ability to drive large capacitive loads. figure 43: "stability criteria with a serial resistor at vdd = 5 v" and figure 44: "stability criteria with a serial resistor at vdd = 1.8 v" show the serial resistor that must be added to the output, to make a system stable. figure 45: "test configuration for riso" shows the test configuration using an isolation resistor, riso. ? v i o ? t ma x v i o t v i o 2 5 C t 2 5 c C = c
tsz121, tsz122, tsz124 application information docid023563 rev 5 21 / 38 figure 43 : stability criteria with a serial resistor at vdd = 5 v figure 44 : stability criteria with a serial resistor at vdd = 1.8 v figure 45 : test configuration for riso 5.8 pcb layout recommendations particular attention must be paid to the layout of the pcb, tracks connected to the amplifier, load, and power supply. the power and ground traces are critical as they must provide adequate energy and grounding for all circuits. good practice is to use short and wide pcb traces to minimize voltage drops and parasitic inductance. in addition, to minimize parasitic impedance over the entire surface, a multi - via technique that connects the bottom and top layer ground planes together in many locations is often used. the copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. 5.9 optimi zed application recommendation tsz121, tsz122, and tsz124 devices are based on chopper architecture. as they are switched devices, it is strongly recommended to place a 0.1 f capacitor as close as possible to the supply pins. a good decoupling has several advantages for an application. first, it helps to reduce electromagnetic interference. due to the modulation of the chopper, the decoupl ing capacitance also helps to reject the small ripple that may appear on the output. tsz121, tsz122, and tsz124 devices have been optimized for use with 10 k in the feedback loop. with this, or a higher value of resistance, these devices offer the best pe rformance.
application information tsz121, tsz122, tsz124 22 / 38 docid023563 rev 5 5.10 emi rejection ration (emirr) the electromagnetic interference (emi) rejection ratio, or emirr, describes the emi immunity of operation al amplifiers. an adverse effect that is common to many op amps is a change in the offset voltage as a result of rf signal rectification. the tsz121, tsz122, and tsz124 have been specially designed to minimize susceptibility to emirr and show an extremely good sensitivity. figure 46: "emirr on in+ pin" shows the emirr in+ of the tsz121, tsz122, and tsz124 measured from 10 mhz up to 2.4 ghz. figure 46 : emirr on in+ pin 5.11 application examples 5.11.1 oxygen sensor the electrochemical sensor creates a current proportional to the concentration of the gas being measured. this current is converted into voltage thanks to r resistance. this voltage is then amplified by tsz121, tsz122, and tsz124 devices (see figure 47: "oxygen sensor principle schematic" ). figure 47 : oxygen sensor principle schematic
tsz121, tsz122, tsz124 application information docid023563 rev 5 23 / 38 the output voltage is calculated using equation 2 : equation 2 as the current delivered by the o2 sensor is extremely low, the impact of the v io can become significant with a traditional operational amplifier. the use of the chopper amplifier of the tsz121, tsz122, or tsz124 is perfect for this application. in additio n, using tsz121, tsz122, or tsz124 devices for the o2 sensor application ensures that the measurement of o2 concentration is stable even at different temperature thanks to a very good v io /t. 5.11.2 precision instrumentation amplifier the instrumentation amplifier uses three op amps. the circuit, shown in figure 48: "precision instrumentation amplifier schematic " , exhibits high input impedance, so that the source impedance of the connected sensor has no impact on the amplification. figure 48 : precision instrumentation amplifier schematic the gain is set by tuning the rg resistor. with r1 = r2 and r3 = r4, the output is given by equation 3 . equation 3 the matching of r1, r2 and r3, r4 is important to ensure a good common mode rejection ratio (cmr). v ou t i r v i o r 2 r 1 1 + C =
application information tsz121, tsz122, tsz124 24 / 38 docid023563 rev 5 5.11.3 low - side current sensing power management mechanisms are found in most electronic systems. current sensing is useful for protecting applications. the low - side current sens ing method consists of placing a sense resistor between the load and the circuit ground. the resulting voltage drop is amplified using tsz121, tsz122, and tsz124 devices (see figure 49: "low - side current sensing schematic" ) . figure 49 : low - side current sensing schematic v out can be expressed as follows: equation 4 assuming that r f2 = r f1 = r f and r g2 = r g1 = r g , equation 4 can be simplified as follows: equation 5 the main advantage of using the chopper of the tsz121, tsz122, and tsz124, for a low - side current sensing, is that the errors due to v io and i io are extremely low and may be neglected. therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. particular attention must be paid on the matching and precision of r g1 , r g2 , r f1 , and r f2 , to maximize the accuracy of the measurement. v o u t r s h un t i r f r g v i o 1 r f r g C r f i i o + = + v ou t r s hun t i 1 r g 2 r g 2 r f 2 + 1 r f 1 r g 1 C i p r g 2 r f 2 r g 2 r f 2 1 r f 1 r g 1 l n r f 1 v i o 1 r f 1 r g 1 + C C + = + + +
tsz121, tsz122, tsz124 packa ge information docid023563 rev 5 25 / 38 6 package informa tion in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information tsz121, tsz122, tsz124 26 / 38 docid023563 rev 5 6.1 sc70 - 5 (or sot323 - 5) package information figure 50 : sc70 - 5 (or sot323 - 5) package outline table 6: sc70 - 5 (or sot323 - 5) mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.80 1.10 0.032 0.043 a1 0.10 0.004 a2 0.80 0.90 1.00 0.032 0.035 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 l 0.26 0.36 0.46 0.010 0.014 0.018 < 0 8 0 8 se a ting plane gauge plane dimensions in mm side view t o p view coplanar leads
tsz121, tsz122, tsz124 package information docid023563 rev 5 27 / 38 6.2 sot23 - 5 package information figure 51 : sot23 - 5 package outline table 7: sot23 - 5 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 1.45 0.057 a1 0.00 0.15 0.000 0.006 a2 1.15 0.90 1.30 0.045 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 d 2.90 0.114 e 2.80 0.110 e1 1.60 0.063 e 0.95 0.037 e1 1.90 0.075 l 0.45 0.30 0.60 0.018 0.012 0.024 s 4 0 8 4 0 8
package information tsz121, tsz122, tsz124 28 / 38 docid023563 rev 5 figure 52 : sot23 - 5 recommended footprint
tsz121, tsz122, tsz124 package information docid023563 rev 5 29 / 38 6.3 dfn8 2x2 package information figure 53 : dfn8 2x2 package outline table 8: dfn8 2x2 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.51 0.55 0.60 0.020 0.022 0.024 a1 0.05 0.002 a3 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 d 1.85 2.00 2.15 0.073 0.079 0.085 d2 1.45 1.60 1.70 0.057 0.063 0.067 e 1.85 2.00 2.15 0.073 0.079 0.085 e2 0.75 0.90 1.00 0.030 0.035 0.039 e 0.50 0.020 l 0.425 0.017 ddd 0.08 0.003
package information tsz121, tsz122, tsz124 30 / 38 docid023563 rev 5 figure 54 : dfn8 2x2 recommended footprint
tsz121, tsz122, tsz124 package information docid023563 rev 5 31 / 38 6.4 miniso8 package information figure 55 : miniso8 package outline table 9: miniso8 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 1.1 0.043 a1 0 0.15 0 0.006 a2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 d 2.80 3.00 3.20 0.11 0.118 0.126 e 4.65 4.90 5.15 0.183 0.193 0.203 e1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 l 0.40 0.60 0.80 0.016 0.024 0.031 l1 0.95 0.037 l2 0.25 0.010 k 0 8 0 8 ccc 0.10 0.004
package information tsz121, tsz122, tsz124 32 / 38 docid023563 rev 5 6.5 so8 package information figure 56 : so8 package outline table 10: so8 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 d 4.80 4.90 5.00 0.189 0.193 0.197 e 5.80 6.00 6.20 0.228 0.236 0.244 e1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 l1 1.04 0.040 k 1 8 1 8 ccc 0.10 0.004
tsz121, tsz122, tsz124 package information docid023563 rev 5 33 / 38 6.6 qfn16 3x3 package information figure 57 : qfn16 3x3 package outline
package information tsz121, tsz122, tsz124 34 / 38 docid023563 rev 5 table 11: qfn16 3x3 mechanical data ref. dimensios millimeters inches min. typ. max. min. typ. max. a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0 0.05 0 0.002 a3 0.20 0.008 b 0.18 0.30 0.007 0.012 d 2.90 3.00 3.10 0.114 0.118 0.122 d2 1.50 1.80 0.059 0.071 e 2.90 3.00 3.10 0.114 0.118 0.122 e2 1.50 1.80 0.059 0.071 e 0.50 0.020 l 0.30 0.50 0.012 0.020 figure 58 : qfn16 3x3 recommended footprint
tsz121, tsz122, tsz124 package information docid023563 rev 5 35 / 38 6.7 tssop14 package information figure 59 : tssop14 package outline table 12: tssop14 mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 1.20 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.90 5.00 5.10 0.193 0.197 0.201 e 6.20 6.40 6.60 0.244 0.252 0.260 e1 4.30 4.40 4.50 0.169 0.173 0.176 e 0.65 0.0256 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 8 0 8 aaa 0.10 0.004 aaa
ordering information tsz121, tsz122, tsz124 36 / 38 docid023563 rev 5 7 ordering information table 13: order codes order code temperature range package packaging marking TSZ121ICT - 40 to 125 c sc70 - 5 tape and reel k44 tsz121ilt s?23 - 5 k143 tsz122iq2t dfn8 2x2 k33 tsz122ist miniso8 k208 tsz122idt so8 tsz122i tsz124iq4t qfn16 3x3 k193 tsz124ipt tssop14 tsz124i tsz121iylt (1) - 40 to 125 c automotive grade s?23 - 5 k192 tsz122iydt (2) so8 k192d tsz122iyst (1) miniso8 k192 tsz124iypt (1) tssop14 tsz124iy notes: (1) qualified and characterized according to aec q100 and q003 or equivalent, advanced screening according to aec q001 & q 002 or equivalent. (2) automotive qualification ongoing
tsz121, tsz122, tsz124 revision history docid023563 rev 5 37 / 38 8 revision history date revision changes 16 - aug - 2012 1 initial release. 25 - apr - 2013 2 added dual and quad products (tsz122 and tsz124 respectively) updated title added following packages: dfn8 2x2, miniso8, qfn16 3x3, tssop14. updated features added benefits and related products updated description updated table 1 (r thja , esd) updated table 3 (v io , ?v io /?t, cmr, a vd , icc, e n , and c s ) updated table 4 (v io , ?v io /?t, cmr, i cc , e n , and c s ) updated table 5 (v io , ?v io /?t, cmr, svr, emirr, i cc , t s , e n , and c s ). updated curves of section 3: electrical characteristics added section 4.7: capacitive load small update section 4.9: optimized application recommendation (capacitor). add ed section 4.10: emi rejection ration (emirr) updated table 10: order codes 11 - sep - 2013 3 added so8 package for commercial part number tsz122idt related products: added hyperlinks for tsv71x and tsv73x products. table 1: updated cdm information figure 6, figure 7: updated x - axes titles figure 12: updated x - axis and y - axis titles figure 19: updated title figure 26: updated x - axis (logarithmic scale) figure 27 and figure 28: updated y - axis titles 23 - may - 2014 4 table 1: updated esd information table 5: added footnote 3 table 10: order codes: added automotive qualification footnotes 1 and 2; updated marking of tsz122ist. updated disclaimer 09 - may - 2016 5 updated document layout table 13: "order codes" : added new automotive grade order code tsz122iyd, updated footnotes of other automotive grade order codes.
tsz121, tsz122, tsz124 38 / 38 docid023563 rev 5 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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